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21
User Guide
COMe-bP5020
B81..
B83
N/C N/C
B84..
B87
VCC_5V_SBY PWR PWR
B88 BIOS_DIS1# BOARD CTRL I-3.3 PU-10k external Boot-Flash Select
B89 JTAG TCK JTAG/PROG I-3.3 series resistor 30R. PD 1k manufacturing use
B90 GND PWR PWR
B91 JTAG TDI JTAG/PROG series resistor 39R, PU 4k7 3.3V manufacturing use
B92 JTAG TMS JTAG/PROG series resistor 39R, PU 4k7 3.3V manufacturing use
B93 JTAG TDO JTAG/PROG series resistor 39R manufacturing use
B94 N/C
B95 Reserved leave unconnected
B96 Reserved leave unconnected
B97 SPI_CS# SPI O-3.3 SPI_CS0# of CPU if BIOS_DIS =
low / SPI_CS2# of CPU if
BIOS_DIS = N/C or high
B98 EMI2_MDC ETH MGT O-1.2 PU 180R 1.2V Ethernet Management Clock for
XAUI usage
B99 EMI2_MDIO ETH MGT I/O-1.2 PU 330R 1.2V Ethernet Management In/Out for
XAUI usage
B100 GND PWR PWR
B101..
B103
N/C N/C
B104..
B109
VCC_12V PWR PWR nominal 12V
B110 GND PWR PWR
Table 6: Connector J2 Row C Pinout
PIN SIGNAL
SIGNAL
GROUP
TYPE TERMINATION COMMENT
C1 GND PWR PWR
C2..
C10
N/C N/C
C11 GND PWR PWR
C12..
C16
N/C N/C
C17 LOE# Local Bus STRAP/
O-3.3
PU 4k7 Local Bus output enable
C18 LWE[0]# Local Bus O-3.3
C19 SERDES_RX6+ SERDES DP-I AC coupled on module (100n) SerDes Bank 1 G
C20 SERDES_RX6- SERDES DP-I AC coupled on module (100n) SerDes Bank 1 G
C21 GND PWR PWR
C22 SERDES_RX7+ SERDES DP-I AC coupled on module (100n) SerDes Bank 1 H
C23 SERDES_RX7- SERDES DP-I AC coupled on module (100n) SerDes Bank 1 H
C24..
C26
N/C N/C
C27 LAD0 Local Bus I/O-3.3 multiplexed CPU address/data signal
Table 5: Connector J1 Row B Pinout (cont’d)
PIN SIGNAL
SIGNAL
GROUP
TYPE TERMINATION COMMENT
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